This invention relates to communication links between central processing units in computing networks and peripheral devices used for inputting and outputting data to and from the central processing unit. More particularly, this invention relates to a method of controlling interrupt signals generated by plural peripheral devices in order to permit the central processing unit to preselect interrupt signals by interrupt classification.
The prior art development of communication networks linking central processing units with plural input and output peripheral devices has developed along two primary paths. In the first of these paths, a central processing unit develops a time sharing system by polling plural remote peripheral devices in a selected sequence, giving each of the peripheral devices an opportunity, in turn, to communicate with the central processing unit. In most such systems, a polling signal is generated at the central processing unit, as by addressing each of the peripherals in turn, so that the data transmission from the peripherals can be synchronized. Such polling systems are inherently inefficient since they require that the central processing unit address peripherals in turn, regardless of whether those peripherals have data to transmit to the central processing unit. Thus, each time that a polling signal is transmitted to a peripheral device which does not require servicing, a wasted communication step is incurred.
In order to overcome this inefficiency, the prior art has developed a peripheral communication scheme based upon interrupts. In such systems the peripheral devices are each associated with a controller which provides an interrupt user request signal to the central processing unit when data is to be supplied to or from the peripheral device. Typically, in response to this interrupt user request, the central processing unit, when time is available for processing the peripheral data, will issue an interrupt address request signal to the controller associated with the requesting peripheral device. In response to this address request, the peripheral controller will typically provide a vector signal on a data bus. This vector signal provides an address for the central processing unit which identifies a location in the memory of the central processing unit. This memory location typically stores the necessary operation codes required for servicing the interrupt signal. The central processing unit, in response to these operation codes, will direct the peripheral device, through its controller, to transmit data on the data bus.
With systems of this latter type, which are based upon peripheral interrupts for servicing peripheral devices, the central processing unit will often include priority logic which will permit the central processing unit to service simultaneously received interrupts in a priority order predetermined on the basis of the class of peripheral devices involved. Such schemes, however, do not permit the preselection of interrupt signals by the central processing unit, so that even those peripheral devices which are not to be serviced by the central processing unit will always, in prior art systems, issue interrupt signals which must be processed and then ignored by the central processing unit. This transmission of interrupt signals without preselection by the central processing unit causes inherent inefficiencies in the system.